With the continuing development of Si technology, the feature size of semiconductors is decreasing, which implies that the possibility of damage from electrostatic discharge (ESD) is becoming increasingly serious. Conventional ESD devices such as diodes or gate grounded N-channel metal oxide semiconductors (GGNMOS) also consume a relatively large silicon area because of their low current capability. Among ESD devices, the low voltage trigger silicon controlled rectifier (LVTSCR) has been considered as an on-chip ESD protection structure because of its lower on-state resistor, high current capability, and low trigger voltage (. When the chip is powered off, the SCR has the strongest ESD robustness in the smallest layout area.^[1] However, particularly for the case of a supply clamp, the low will prevent the structure from turning off after the ESD pulse. The transient-induced latch-up effect is a fatal defect, which affects the reliability of ICs. Moreover, the error triggered by the noises^[2] also affects the stability of the IC. If the of the SCR is higher than the normal supply voltage, it will be free of such issues.^[2] The methods to improve the of SCRs have motivated many research teams.^[3–17] One method is the segmented technique, which was proposed in Refs. [3] and [14] to reduce the emitter injection efficiency. The can be adjusted by optimizing the N+/P+ ratio. However, the is decreased, because the higher leads to a higher generation of heat under the same current distribution. The stacking technique was proposed in Refs. [6] and [8]. It can improve the linearly by increasing the number of unit devices. However, it not only needs a trigger circuit to ensure an acceptable but also requires more stacking units to achieve a higher . The huge chip area occupation makes it unsuitable for use in high voltage ICs. The emitter voltage clamp is a good way to improve the without additional masks under the same technological processes.^[5] However, the non-adjustability of is a limitation.

In this paper, a novel high SCR, which features a long N+ (LN+) layer and a long P+ (LP+) layer is proposed. In the low condition, the LN+ layer and the LP+ layer form two high concentration base regions of parasitic NPN and PNP, which decrease the current gain of SCR2 to improve the . In the high condition, the low current gain of SCR2 restrains the surface current and extends the ESD path of SCR1, which induces the second snapback with high . As the deeper current path avoids surface current crowding, a strong ESD robustness can be obtained. Moreover, the device is entirely compatible with the technology of LVTSCRs without additional masks or process steps.

Figures 1(a) and 1(b) show the schematic cross-sectional view of the conventional LVTSCR and its layout diagram. With the increase in the ESD voltage at the anode, the breakdown of the drain PN junction of the parasitic GGNMOS (M1) enhances the trigger speed, then the avalanche current triggers the parasitic transistors (Q1 and Q2) by the parasitic resistors (R1 and R2). The strong positive feedback of the PNP and NPN causes strong snapback with a low (about 1–2 V). Due to the low , the LVTSCR cannot be used in the power clamp of the chip because of its huge risk of the latch-up effect occurring and the error trigger issue.

Fig. 1.

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	Fig. 1. (color online) (a) Cross-sectional view of the LVTSCR, (b) the layout diagram of LVTSCR, (c) the cross-sectional view of the proposed SCR, and (d) the layout diagram of the proposed SCR.

In order to prevent the aforementioned issues, a novel SCR is proposed in this paper. Figures 1(c) and 1(d) show the schematic cross-sectional view of the proposed SCR and its layout diagram. The proposed SCR features an LN+ layer and an LP+ layer, which constitute two high concentration base regions of parasitic PNP and NPN. In the low condition, the SCR1 and SCR2 are turned on; the two high concentration base regions decrease the current gain of SCR2 and weaken its positive feedback. Therefore, the first snapback needs to have a high to maintain the two SCRs. With the increase in , the low current gain of SCR2 causes its turn-off. The majority of the current will flow through the longer SCR1 path bypassing SCR2, which induces the second snapback with high . Meanwhile, the breakdown of the LN+/PWELL junction also reduces the breakdown voltage (BV) to ensure an acceptable .

To discuss the I–V characteristics, ESD-induced latch-up effect, and the pulse performance, the direct current (DC), dynamic TLP-like (transmission line pulse-like), and TLP multiple-pulse simulations^[18–20] have been used. Figure 2 shows the dynamic TLP-like simulation and TLP multiple-pulse simulation circuit. Dynamic TLP-like simulation means a voltage pulse, which is like a TLP pulse, is applied to the anode of an LVTSCR or proposed SCR through a resistor with the anode DC voltage ( equal to VDD, then a -time curve, which contains the latch-up information, can be obtained. The TLP multiple-pulse simulation is similar to the actual TLP test: a series of current pulses with increasing amplitude, 10 ns of rise time, 100 ns of duration time, and 10 ns of fall time are applied to both ends of an LVTSCR or proposed SCR. Then, a series of voltage pulses can be obtained. Each current pulse and the average of 70–90% of the corresponding voltage will constitute a point on the TLP I–V curve. By linking the series of points with a line, the TLP I–V curve will be achieved. The main parameters of the proposed SCR are listed in Table 1.

Fig. 2.

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	Fig. 2. (color online) (a) Dynamic TLP-like simulation circuit with , and (b) TLP multiple-pulse simulation circuit.

Table 1.

Table 1.

Table 1. The main parameters of the proposed SCR. . Device parameters Proposed SCR Length The length of L1/L3 The length of L2 NWELL concentration 5 × 1016 cm−3 P-sub concentration 1 × 1015 cm−3

Table 1. The main parameters of the proposed SCR. .

The DC simulation results of the LVTSCR and proposed SCR with and are shown in Fig. 3. The of the LVTSCR is 1.3 V and that of the proposed SCR is 7.4 V. In the low condition, the SCR1 and SCR2 are triggered together, which need a high holding voltage () to maintain the two ESD paths. As the increases to second holding current (, the SCR2 has been turned off. At this time, the SCR1 is the main path to discharge the . Because the SCR1 has the longer current path, the second holding voltage ( will be decreased from 15 V ( to 7.4 V instead of 1.3 V. Meanwhile, the of the proposed SCR is still close to that of the LVTSCR.

Fig. 3.

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	Fig. 3. (color online) DC simulation results of LVTSCR and proposed SCR with and .

According to the above theories, the of the proposed SCR can be adjusted by changing L₁ and L₃. Under smaller L₁ or L₃, more holes (electrons) are injected into the LN+ layer (LP+ layer), which will induce a higher . In addition, the longer ESD current path and the higher can be obtained by decreasing L₁ or L₃. Figure 4 shows the snapback I–V curves with various L₁ and L₃. These results prove the double snapback characteristic. The highest of 14.6 V and of 16.2 V with and are obtained. When , : it increases up to 12.9 V when L₁ and L₃ decrease to 0.1 . When L₁ is fixed, the will decrease with the increase in L₃. Moreover, the double snapback characteristic of the proposed SCR with will disappear because increases up to a high value, which is close to , due to the longer ESD path. The is less sensitive to L₁ and L₃.

Fig. 4.

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	Fig. 4. (color online) (a) Snapback I–V curves of the proposed SCR with increasing from 0.1 to , (b) snapback I–V curves of the proposed SCR with increasing from 0.1 to .

The TLP multiple-pulse simulation has been used to analyse the pulse snapback characteristics of the LVTSCR and proposed SCR with L₁ and L₃ increasing from 0.1 to . Figures 5(a) and 5(b) show the voltage response of the LVTSCR and TLP I–V curves of all SCRs when the width of the device is . The of the LVTSCR is only 1.9 V, which is far less than the highest of 12.5 V with . The will decrease to 11 V with L₁ and L₃ increasing from to . Meanwhile, the double snapbacks characteristic also occurs in the devices with and . The TLP multiple-pulse simulation shows the same trends as the DC simulation.

Fig. 5.

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	Fig. 5. (color online) (a) Example of voltage response of LVTSCR, and (b) simulated TLP I–V curves of the proposed SCR with L1 and L3 increasing from 0.1 to . (c) Depletion region distributions of proposed SCR and (d) LVTSCR.

Figure 5(b) shows the of the proposed SCRs have some decreases, which are ascribed to the high concentration of the LP+ layer. The LP+ layer obstructs the depletion region extension and reduces the breakdown voltage (BV). The simulated depletion regions are shown in Figs. 5(c) and 5(d). Figure 5(c) shows that the depletion region of the proposed SCR is obstructed on the left edge of the LP+. The avalanche breakdown of the PN junction which is formed by the LN+, P-sub, and LP+ in the proposed SCR happens easier than that of the LVTSCR, which induces the reduction.

In order to analyse the transient-induced latch-up issue during normal operation, a dynamic TLP-like simulation circuit has been used. The time-domain results are shown in Fig. 6. After transient triggering, the latch-up effect may happen in the LVTSCR. The voltage is clamped down to V and the latch-up current ( is 0.17 A. In contrast, the voltage of the proposed SCR is still kept at 7 V, and the is 0 A after the same transient pulse during normal operation in the 7 V circuit. These results prove that the proposed SCR is a high latch-up-free device for 7 V circuit ESD applications.

Fig. 6.

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	Fig. 6. (color online) (a) Voltage responses of LVTSCR and the proposed SCR with various L1 and L3 in 7-V circuit and (b) their corresponding current responses.

The maximum failure power dissipation of the ESD device can be given by Eq. (1). The higher will cause a higher power dissipation, which leads to the lower . Therefore, the proposed SCR with V (, ) is the best choice to alleviate the contradiction between and in the 7 V circuit. Moreover, the hot area which is formed by current crowding on the right edge of the anode P+ region further causes the decrease in . The deeper current instead of a surface current can restrain the hot area forming and improve . The proposed SCR has a deeper ESD path, which will induce the lower surface temperature. Hence, it is very suitable as a device for a high level of ESD protection

Fig. 7.

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	Fig. 7. (color online) Simulated current distributions of the proposed SCR with , under (a) , (b) , and (c) . (d) Simulated current distributions of LVTSCR under .

Fig. 8.

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	Fig. 8. (color online) (a) Simulated surface temperature distributions of LVTSCR (b) and the proposed SCR with , , (c) their – curves, and (d) their on-state ESD limitation curves.

The concerned parameters are contrasted in Table 2. According to the data in Table 2, the compared SCR with , has the higher . The of 7.4 V can avoid the transient-induced latch-up effect in the 7 V circuit. Moreover, the of the compared SCR is 16.1 V, which provides the same trigger speed as the LVTSCR. The higher () is also obtained in the compared SCR. The comparison of the results shows that the compared SCR is more suitable than the LVTSCR to be used in latch-up-free robustness ESD application.

Table 2.

Table 2.

Table 2. The parameters comparison between LVTSCR and proposed SCR. .   LVTSCR Proposed SCR     (, ) /V 16.1 16.1 /V 1.3 7.4

Table 2. The parameters comparison between LVTSCR and proposed SCR. .

In this paper, we propose a high holding voltage SCR with an LN+ layer and an LP+ layer for ESD protection application, and investigate its latch-up effect, current, temperature distribution, and power limitation. A of 7.4 V and of 16.1 V were obtained by optimizing the lengths of L₁ and L₃. The can be adjusted from 6.1 V to 14.6 V by changing the lengths of LN+ and LP+ (L₁ and . According to the simulated results, the proposed SCR can effectively avoid the latch-up effect without causing any degradation in its ESD robustness () and improve the from to without additional masks or process steps.